[TUHS] Split addressing (I/D) space (inspired by the death of the python... thread)
Noel Chiappa
jnc at mercury.lcs.mit.edu
Fri Aug 4 07:48:21 AEST 2023
> From: Will Senn
> Does unix (v7) know about the PDP-11 45's split I/D space through
> configuration or is it convention and programmer's responsibility to
> know and manage what's actually available?
There are two different cases: i) support of split I+D in the kernel, and
ii) support of split I+D in user processes. Both arrived with V6; the
V5 source:
https://minnie.tuhs.org/cgi-bin/utree.pl?file=V5/usr/sys/conf/mch.s
https://minnie.tuhs.org/cgi-bin/utree.pl?file=V5/usr/sys/ken/main.c
(former for kernel; later for users) shows no sign of it.
> From: Kenneth Goodwin <kennethgoodwin56 at gmail.com>
> 1. I don't think the 11/45 had split I & d.
> But I could be wrong.
> That did not appear until the 11/70
You are wrong.
The chief differences between the KB11-A&-D of the -11/45 and the -B&-C of
the -11/70 were i) the latter had a cache, and ii) the latter used the 32-bit
wide Main Memory Bus, which also allowed up to 4 Mbytes of main memory.
Detail here:
https://gunkies.org/wiki/PDP-11/70
along with a couple of lesser differences.
> From: "Ronald Natalie"
> with only 8 segment registers combined for code, data, and stack
I think you meant for code, data, and user block.
> The 55 (just a tweaked 45)
The /50 and /55 had the identical KB11-A&-D of the /45; the difference was
that they came pre-configured with Fastbus memory.
> In addition the 23/24/J-11 and those derived processors did.
No; the F-11 processors did not support I&D, the J-11 did.
Noel
More information about the TUHS
mailing list