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<p>Any CPU with only a byte-wide memory interface (e.g. 8088)
doesn't care about bigger word alignments. But yes, if the CPU can
do 16 and 32 and 64 bits at a time, then aligned accesses of
bigger words can be one transaction instead of two.<br>
</p>
<div class="moz-cite-prefix">On 03/03/2025 03:00 PM, Paul Winalski
wrote:<br>
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<blockquote
cite="mid:CABH=_VS53kAycHGOY2YrKTbqNCpwcvc_hWi_zPMgbhhMcBN-Rw@mail.gmail.com"
type="cite">
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<div dir="ltr">On Mon, Mar 3, 2025 at 1:28 PM Larry McVoy <<a
moz-do-not-send="true" href="mailto:lm@mcvoy.com">lm@mcvoy.com</a>>
wrote:</div>
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<blockquote class="gmail_quote" style="margin:0px 0px 0px
0.8ex;border-left:1px solid
rgb(204,204,204);padding-left:1ex"><br>
Even x86, it would appear, wants to do aligned loads. I'm a
little<br>
surprised by that though maybe I shouldn't be as there is a
RISC<br>
implemented by the microcode under the x86 CPU.<br>
<br>
</blockquote>
<div>I don't think there's ever been a CPU design where
unaligned accesses run at the same speed as naturally
aligned accesses. The worst case is an unaligned access
that straddles a machine-word boundary.</div>
<div><br>
</div>
<div>-Paul W.<br>
</div>
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