FAS on a Microchannel Box with Xenix

[Ronald Florence]

gemini at geminix.in-berlin.de (Uwe Doering) writes:

 > This means that there are no NS16550A chips on the main board and the
 > first dual-asynch board. 

The UART on the motherboard and the UARTs on the first dual-asynch
board are NS16550s.  The first dual-asynch board is identical to the
the one which does show up as FIFO-capable.

 > Your space.c seems to be o.k. Did you enter the following line in
 > /usr/sys/conf/master?
 > 
 > 	sio      4  0537 104    fas  0   0   5    1   7    3     4     33   34  
Yes.  And I ran configure after making the changes.

 > If this doesn't work the only reason for your problems I can think of is
 > the different handling of interrupts. On the AT bus interrupts are edge
 > triggered while on the micro channel they are level triggered. Maybe this
 > breaks FAS' interrupt handler.

Thanks to Uwe for his prompt response, and to all for any further
suggestions on getting FAS to run on a microchannel system.
--

Ronald Florence			{hsi,rayssd}!mlfarm!ron