Net2/usr/src/usr.bin/gcc/doc/gcc.info-6
Info file gcc.info, produced by Makeinfo, -*- Text -*- from input
file gcc.texinfo.
This file documents the use and the internals of the GNU compiler.
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File: gcc.info, Node: Arithmetic, Next: Comparisons, Prev: Regs and Memory, Up: RTL
RTL Expressions for Arithmetic
==============================
`(plus:M X Y)'
Represents the sum of the values represented by X and Y carried
out in machine mode M. This is valid only if X and Y both are
valid for mode M.
`(minus:M X Y)'
Like `plus' but represents subtraction.
`(compare X Y)'
Represents the result of subtracting Y from X for purposes of
comparison. The absence of a machine mode in the `compare'
expression indicates that the result is computed without
overflow, as if with infinite precision.
Of course, machines can't really subtract with infinite precision.
However, they can pretend to do so when only the sign of the
result will be used, which is the case when the result is stored
in `(cc0)'. And that is the only way this kind of expression
may validly be used: as a value to be stored in the condition
codes.
`(neg:M X)'
Represents the negation (subtraction from zero) of the value
represented by X, carried out in mode M. X must be valid for
mode M.
`(mult:M X Y)'
Represents the signed product of the values represented by X and
Y carried out in machine mode M. If X and Y are both valid for
mode M, this is ordinary size-preserving multiplication.
Alternatively, both X and Y may be valid for a different,
narrower mode. This represents the kind of multiplication that
generates a product wider than the operands. Widening
multiplication and same-size multiplication are completely
distinct and supported by different machine instructions;
machines may support one but not the other.
`mult' may be used for floating point multiplication as well.
Then M is a floating point machine mode.
`(umult:M X Y)'
Like `mult' but represents unsigned multiplication. It may be
used in both same-size and widening forms, like `mult'. `umult'
is used only for fixed-point multiplication.
`(div:M X Y)'
Represents the quotient in signed division of X by Y, carried
out in machine mode M. If M is a floating-point mode, it
represents the exact quotient; otherwise, the integerized
quotient. If X and Y are both valid for mode M, this is
ordinary size-preserving division. Some machines have division
instructions in which the operands and quotient widths are not
all the same; such instructions are represented by `div'
expressions in which the machine modes are not all the same.
`(udiv:M X Y)'
Like `div' but represents unsigned division.
`(mod:M X Y)'
`(umod:M X Y)'
Like `div' and `udiv' but represent the remainder instead of the
quotient.
`(not:M X)'
Represents the bitwise complement of the value represented by X,
carried out in mode M, which must be a fixed-point machine mode.
x must be valid for mode M, which must be a fixed-point mode.
`(and:M X Y)'
Represents the bitwise logical-and of the values represented by
X and Y, carried out in machine mode M. This is valid only if X
and Y both are valid for mode M, which must be a fixed-point mode.
`(ior:M X Y)'
Represents the bitwise inclusive-or of the values represented by
X and Y, carried out in machine mode M. This is valid only if X
and Y both are valid for mode M, which must be a fixed-point mode.
`(xor:M X Y)'
Represents the bitwise exclusive-or of the values represented by
X and Y, carried out in machine mode M. This is valid only if X
and Y both are valid for mode M, which must be a fixed-point mode.
`(lshift:M X C)'
Represents the result of logically shifting X left by C places.
X must be valid for the mode M, a fixed-point machine mode. C
must be valid for a fixed-point mode; which mode is determined
by the mode called for in the machine description entry for the
left-shift instruction. For example, on the Vax, the mode of C
is `QImode' regardless of M.
On some machines, negative values of C may be meaningful; this
is why logical left shift and arithmetic left shift are
distinguished. For example, Vaxes have no right-shift
instructions, and right shifts are represented as left-shift
instructions whose counts happen to be negative constants or
else computed (in a previous instruction) by negation.
`(ashift:M X C)'
Like `lshift' but for arithmetic left shift.
`(lshiftrt:M X C)'
`(ashiftrt:M X C)'
Like `lshift' and `ashift' but for right shift.
`(rotate:M X C)'
`(rotatert:M X C)'
Similar but represent left and right rotate.
`(abs:M X)'
Represents the absolute value of X, computed in mode M. X must
be valid for M.
`(sqrt:M X)'
Represents the square root of X, computed in mode M. X must be
valid for M. Most often M will be a floating point mode.
`(ffs:M X)'
Represents one plus the index of the least significant 1-bit in
X, represented as an integer of mode M. (The value is zero if X
is zero.) The mode of X need not be M; depending on the target
machine, various mode combinations may be valid.
File: gcc.info, Node: Comparisons, Next: Bit Fields, Prev: Arithmetic, Up: RTL
Comparison Operations
=====================
Comparison operators test a relation on two operands and are
considered to represent a machine-dependent nonzero value
(`STORE_FLAG_VALUE') if the relation holds, or zero if it does not.
The mode of the comparison is determined by the operands; they must
both be valid for a common machine mode. A comparison with both
operands constant would be invalid as the machine mode could not be
deduced from it, but such a comparison should never exist in RTL due
to constant folding.
Inequality comparisons come in two flavors, signed and unsigned.
Thus, there are distinct expression codes `gt' and `gtu' for signed
and unsigned greater-than. These can produce different results for
the same pair of integer values: for example, 1 is signed
greater-than -1 but not unsigned greater-than, because -1 when
regarded as unsigned is actually `0xffffffff' which is greater than 1.
The signed comparisons are also used for floating point values.
Floating point comparisons are distinguished by the machine modes of
the operands.
The comparison operators may be used to compare the condition codes
`(cc0)' against zero, as in `(eq (cc0) (const_int 0))'. Such a
construct actually refers to the result of the preceding instruction
in which the condition codes were set. The above example stands for
1 if the condition codes were set to say "zero" or "equal", 0
otherwise. Although the same comparison operators are used for this
as may be used in other contexts on actual data, no confusion can
result since the machine description would never allow both kinds of
uses in the same context.
`(eq X Y)'
1 if the values represented by X and Y are equal, otherwise 0.
`(ne X Y)'
1 if the values represented by X and Y are not equal, otherwise 0.
`(gt X Y)'
1 if the X is greater than Y. If they are fixed-point, the
comparison is done in a signed sense.
`(gtu X Y)'
Like `gt' but does unsigned comparison, on fixed-point numbers
only.
`(lt X Y)'
`(ltu X Y)'
Like `gt' and `gtu' but test for "less than".
`(ge X Y)'
`(geu X Y)'
Like `gt' and `gtu' but test for "greater than or equal".
`(le X Y)'
`(leu X Y)'
Like `gt' and `gtu' but test for "less than or equal".
`(if_then_else COND THEN ELSE)'
This is not a comparison operation but is listed here because it
is always used in conjunction with a comparison operation. To
be precise, COND is a comparison expression. This expression
represents a choice, according to COND, between the value
represented by THEN and the one represented by ELSE.
On most machines, `if_then_else' expressions are valid only to
express conditional jumps.
File: gcc.info, Node: Bit Fields, Next: Conversions, Prev: Comparisons, Up: RTL
Bit-fields
==========
Special expression codes exist to represent bit-field instructions.
These types of expressions are lvalues in RTL; they may appear on the
left side of an assignment, indicating insertion of a value into the
specified bit field.
`(sign_extract:SI LOC SIZE POS)'
This represents a reference to a sign-extended bit-field
contained or starting in LOC (a memory or register reference).
The bit field is SIZE bits wide and starts at bit POS. The
compilation option `BITS_BIG_ENDIAN' says which end of the
memory unit POS counts from.
Which machine modes are valid for LOC depends on the machine,
but typically LOC should be a single byte when in memory or a
full word in a register.
`(zero_extract:SI LOC SIZE POS)'
Like `sign_extract' but refers to an unsigned or zero-extended
bit field. The same sequence of bits are extracted, but they
are filled to an entire word with zeros instead of by
sign-extension.
File: gcc.info, Node: Conversions, Next: RTL Declarations, Prev: Bit Fields, Up: RTL
Conversions
===========
All conversions between machine modes must be represented by explicit
conversion operations. For example, an expression which is the sum
of a byte and a full word cannot be written as `(plus:SI (reg:QI 34)
(reg:SI 80))' because the `plus' operation requires two operands of
the same machine mode. Therefore, the byte-sized operand is enclosed
in a conversion operation, as in
(plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80))
The conversion operation is not a mere placeholder, because there may
be more than one way of converting from a given starting mode to the
desired final mode. The conversion operation code says how to do it.
`(sign_extend:M X)'
Represents the result of sign-extending the value X to machine
mode M. M must be a fixed-point mode and X a fixed-point value
of a mode narrower than M.
`(zero_extend:M X)'
Represents the result of zero-extending the value X to machine
mode M. M must be a fixed-point mode and X a fixed-point value
of a mode narrower than M.
`(float_extend:M X)'
Represents the result of extending the value X to machine mode
M. M must be a floating point mode and X a floating point value
of a mode narrower than M.
`(truncate:M X)'
Represents the result of truncating the value X to machine mode
M. M must be a fixed-point mode and X a fixed-point value of a
mode wider than M.
`(float_truncate:M X)'
Represents the result of truncating the value X to machine mode
M. M must be a floating point mode and X a floating point value
of a mode wider than M.
`(float:M X)'
Represents the result of converting fixed point value X,
regarded as signed, to floating point mode M.
`(unsigned_float:M X)'
Represents the result of converting fixed point value X,
regarded as unsigned, to floating point mode M.
`(fix:M X)'
When M is a fixed point mode, represents the result of
converting floating point value X to mode M, regarded as signed.
How rounding is done is not specified, so this operation may be
used validly in compiling C code only for integer-valued operands.
`(unsigned_fix:M X)'
Represents the result of converting floating point value X to
fixed point mode M, regarded as unsigned. How rounding is done
is not specified.
`(fix:M X)'
When M is a floating point mode, represents the result of
converting floating point value X (valid for mode M) to an
integer, still represented in floating point mode M, by rounding
towards zero.
File: gcc.info, Node: RTL Declarations, Next: Side Effects, Prev: Conversions, Up: RTL
Declarations
============
Declaration expression codes do not represent arithmetic operations
but rather state assertions about their operands.
`(strict_low_part (subreg:M (reg:N R) 0))'
This expression code is used in only one context: operand 0 of a
`set' expression. In addition, the operand of this expression
must be a `subreg' expression.
The presence of `strict_low_part' says that the part of the
register which is meaningful in mode N, but is not part of mode
M, is not to be altered. Normally, an assignment to such a
subreg is allowed to have undefined effects on the rest of the
register when M is less than a word.
File: gcc.info, Node: Side Effects, Next: Incdec, Prev: RTL Declarations, Up: RTL
Side Effect Expressions
=======================
The expression codes described so far represent values, not actions.
But machine instructions never produce values; they are meaningful
only for their side effects on the state of the machine. Special
expression codes are used to represent side effects.
The body of an instruction is always one of these side effect codes;
the codes described above, which represent values, appear only as the
operands of these.
`(set LVAL X)'
Represents the action of storing the value of X into the place
represented by LVAL. LVAL must be an expression representing a
place that can be stored in: `reg' (or `subreg' or
`strict_low_part'), `mem', `pc' or `cc0'.
If LVAL is a `reg', `subreg' or `mem', it has a machine mode;
then X must be valid for that mode.
If LVAL is a `reg' whose machine mode is less than the full
width of the register, then it means that the part of the
register specified by the machine mode is given the specified
value and the rest of the register receives an undefined value.
Likewise, if LVAL is a `subreg' whose machine mode is narrower
than `SImode', the rest of the register can be changed in an
undefined way.
If LVAL is a `strict_low_part' of a `subreg', then the part of
the register specified by the machine mode of the `subreg' is
given the value X and the rest of the register is not changed.
If LVAL is `(cc0)', it has no machine mode, and X may have any
mode. This represents a "test" or "compare" instruction.
If LVAL is `(pc)', we have a jump instruction, and the
possibilities for X are very limited. It may be a `label_ref'
expression (unconditional jump). It may be an `if_then_else'
(conditional jump), in which case either the second or the third
operand must be `(pc)' (for the case which does not jump) and
the other of the two must be a `label_ref' (for the case which
does jump). X may also be a `mem' or `(plus:SI (pc) Y)', where
Y may be a `reg' or a `mem'; these unusual patterns are used to
represent jumps through branch tables.
`(return)'
Represents a return from the current function, on machines where
this can be done with one instruction, such as Vaxes. On
machines where a multi-instruction "epilogue" must be executed
in order to return from the function, returning is done by
jumping to a label which precedes the epilogue, and the `return'
expression code is never used.
`(call FUNCTION NARGS)'
Represents a function call. FUNCTION is a `mem' expression
whose address is the address of the function to be called.
NARGS is an expression which can be used for two purposes: on
some machines it represents the number of bytes of stack
argument; on others, it represents the number of argument
registers.
Each machine has a standard machine mode which FUNCTION must
have. The machine description defines macro `FUNCTION_MODE' to
expand into the requisite mode name. The purpose of this mode
is to specify what kind of addressing is allowed, on machines
where the allowed kinds of addressing depend on the machine mode
being addressed.
`(clobber X)'
Represents the storing or possible storing of an unpredictable,
undescribed value into X, which must be a `reg' or `mem'
expression.
One place this is used is in string instructions that store
standard values into particular hard registers. It may not be
worth the trouble to describe the values that are stored, but it
is essential to inform the compiler that the registers will be
altered, lest it attempt to keep data in them across the string
instruction.
X may also be null--a null C pointer, no expression at all.
Such a `(clobber (null))' expression means that all memory
locations must be presumed clobbered.
Note that the machine description classifies certain hard
registers as "call-clobbered". All function call instructions
are assumed by default to clobber these registers, so there is
no need to use `clobber' expressions to indicate this fact.
Also, each function call is assumed to have the potential to
alter any memory location, unless the function is declared
`const'.
When a `clobber' expression for a register appears inside a
`parallel' with other side effects, GNU CC guarantees that the
register is unoccupied both before and after that insn.
Therefore, it is safe for the assembler code produced by the
insn to use the register as a temporary. You can clobber either
a specific hard register or a pseudo register; in the latter
case, GNU CC will allocate a hard register that is available
there for use as a temporary.
If you clobber a pseudo register in this way, use a pseudo
register which appears nowhere else--generate a new one each
time. Otherwise, you may confuse CSE.
There is one other known use for clobbering a pseudo register in
a `parallel': when one of the input operands of the insn is also
clobbered by the insn. In this case, using the same pseudo
register in the clobber and elsewhere in the insn produces the
expected results.
`(use X)'
Represents the use of the value of X. It indicates that the
value in X at this point in the program is needed, even though
it may not be apparent why this is so. Therefore, the compiler
will not attempt to delete previous instructions whose only
effect is to store a value in X. X must be a `reg' expression.
`(parallel [X0 X1 ...])'
Represents several side effects performed in parallel. The
square brackets stand for a vector; the operand of `parallel' is
a vector of expressions. X0, X1 and so on are individual side
effect expressions--expressions of code `set', `call', `return',
`clobber' or `use'.
"In parallel" means that first all the values used in the
individual side-effects are computed, and second all the actual
side-effects are performed. For example,
(parallel [(set (reg:SI 1) (mem:SI (reg:SI 1)))
(set (mem:SI (reg:SI 1)) (reg:SI 1))])
says unambiguously that the values of hard register 1 and the
memory location addressed by it are interchanged. In both
places where `(reg:SI 1)' appears as a memory address it refers
to the value in register 1 *before* the execution of the insn.
It follows that it is *incorrect* to use `parallel' and expect
the result of one `set' to be available for the next one. For
example, people sometimes attempt to represent a jump-if-zero
instruction this way:
(parallel [(set (cc0) (reg:SI 34))
(set (pc) (if_then_else
(eq (cc0) (const_int 0))
(label_ref ...)
(pc)))])
But this is incorrect, because it says that the jump condition
depends on the condition code value *before* this instruction,
not on the new value that is set by this instruction.
Peephole optimization, which takes place in together with final
assembly code output, can produce insns whose patterns consist
of a `parallel' whose elements are the operands needed to output
the resulting assembler code--often `reg', `mem' or constant
expressions. This would not be well-formed RTL at any other
stage in compilation, but it is ok then because no further
optimization remains to be done. However, the definition of the
macro `NOTICE_UPDATE_CC' must deal with such insns if you define
any peephole optimizations.
`(sequence [INSNS ...])'
Represents a sequence of insns. Each of the INSNS that appears
in the vector is suitable for appearing in the chain of insns,
so it must be an `insn', `jump_insn', `call_insn', `code_label',
`barrier' or `note'.
A `sequence' RTX never appears in an actual insn. It represents
the sequence of insns that result from a `define_expand'
*before* those insns are passed to `emit_insn' to insert them in
the chain of insns. When actually inserted, the individual
sub-insns are separated out and the `sequence' is forgotten.
Three expression codes appear in place of a side effect, as the body
of an insn, though strictly speaking they do not describe side
effects as such:
`(asm_input S)'
Represents literal assembler code as described by the string S.
`(addr_vec:M [LR0 LR1 ...])'
Represents a table of jump addresses. The vector elements LR0,
etc., are `label_ref' expressions. The mode M specifies how
much space is given to each address; normally M would be `Pmode'.
`(addr_diff_vec:M BASE [LR0 LR1 ...])'
Represents a table of jump addresses expressed as offsets from
BASE. The vector elements LR0, etc., are `label_ref'
expressions and so is BASE. The mode M specifies how much space
is given to each address-difference.
File: gcc.info, Node: Incdec, Next: Assembler, Prev: Side Effects, Up: RTL
Embedded Side-Effects on Addresses
==================================
Four special side-effect expression codes appear as memory addresses.
`(pre_dec:M X)'
Represents the side effect of decrementing X by a standard
amount and represents also the value that X has after being
decremented. X must be a `reg' or `mem', but most machines
allow only a `reg'. M must be the machine mode for pointers on
the machine in use. The amount X is decremented by is the
length in bytes of the machine mode of the containing memory
reference of which this expression serves as the address. Here
is an example of its use:
(mem:DF (pre_dec:SI (reg:SI 39)))
This says to decrement pseudo register 39 by the length of a
`DFmode' value and use the result to address a `DFmode' value.
`(pre_inc:M X)'
Similar, but specifies incrementing X instead of decrementing it.
`(post_dec:M X)'
Represents the same side effect as `pre_dec' but a different
value. The value represented here is the value X has before
being decremented.
`(post_inc:M X)'
Similar, but specifies incrementing X instead of decrementing it.
These embedded side effect expressions must be used with care.
Instruction patterns may not use them. Until the `flow' pass of the
compiler, they may occur only to represent pushes onto the stack.
The `flow' pass finds cases where registers are incremented or
decremented in one instruction and used as an address shortly before
or after; these cases are then transformed to use pre- or
post-increment or -decrement.
Explicit popping of the stack could be represented with these
embedded side effect operators, but that would not be safe; the
instruction combination pass could move the popping past pushes, thus
changing the meaning of the code.
An instruction that can be represented with an embedded side effect
could also be represented using `parallel' containing an additional
`set' to describe how the address register is altered. This is not
done because machines that allow these operations at all typically
allow them wherever a memory address is called for. Describing them
as additional parallel stores would require doubling the number of
entries in the machine description.
File: gcc.info, Node: Assembler, Next: Insns, Prev: IncDec, Up: RTL
Assembler Instructions as Expressions
=====================================
The RTX code `asm_operands' represents a value produced by a
user-specified assembler instruction. It is used to represent an
`asm' statement with arguments. An `asm' statement with a single
output operand, like this:
asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z));
is represented using a single `asm_operands' RTX which represents the
value that is stored in `outputvar':
(set RTX-FOR-OUTPUTVAR
(asm_operands "foo %1,%2,%0" "a" 0
[RTX-FOR-ADDITION-RESULT RTX-FOR-*Z]
[(asm_input:M1 "g")
(asm_input:M2 "di")]))
Here the operands of the `asm_operands' RTX are the assembler
template string, the output-operand's constraint, the index-number of
the output operand among the output operands specified, a vector of
input operand RTX's, and a vector of input-operand modes and
constraints. The mode M1 is the mode of the sum `x+y'; M2 is that of
`*z'.
When an `asm' statement has multiple output values, its insn has
several such `set' RTX's inside of a `parallel'. Each `set' contains
a `asm_operands'; all of these share the same assembler template and
vectors, but each contains the constraint for the respective output
operand. They are also distinguished by the output-operand index
number, which is 0, 1, ... for successive output operands.
File: gcc.info, Node: Insns, Next: Calls, Prev: Assembler, Up: RTL
Insns
=====
The RTL representation of the code for a function is a doubly-linked
chain of objects called "insns". Insns are expressions with special
codes that are used for no other purpose. Some insns are actual
instructions; others represent dispatch tables for `switch'
statements; others represent labels to jump to or various sorts of
declarative information.
In addition to its own specific data, each insn must have a unique
id-number that distinguishes it from all other insns in the current
function, and chain pointers to the preceding and following insns.
These three fields occupy the same position in every insn,
independent of the expression code of the insn. They could be
accessed with `XEXP' and `XINT', but instead three special macros are
always used:
`INSN_UID (I)'
Accesses the unique id of insn I.
`PREV_INSN (I)'
Accesses the chain pointer to the insn preceding I. If I is the
first insn, this is a null pointer.
`NEXT_INSN (I)'
Accesses the chain pointer to the insn following I. If I is the
last insn, this is a null pointer.
The `NEXT_INSN' and `PREV_INSN' pointers must always correspond: if
INSN is not the first insn,
NEXT_INSN (PREV_INSN (INSN)) == INSN
is always true.
Every insn has one of the following six expression codes:
`insn'
The expression code `insn' is used for instructions that do not
jump and do not do function calls. Insns with code `insn' have
four additional fields beyond the three mandatory ones listed
above. These four are described in a table below.
`jump_insn'
The expression code `jump_insn' is used for instructions that
may jump (or, more generally, may contain `label_ref'
expressions). `jump_insn' insns have the same extra fields as
`insn' insns, accessed in the same way. If there is an
instruction to return from the current function, it is recorded
as a `jump_insn'.
`call_insn'
The expression code `call_insn' is used for instructions that
may do function calls. It is important to distinguish these
instructions because they imply that certain registers and
memory locations may be altered unpredictably.
`call_insn' insns have the same extra fields as `insn' insns,
accessed in the same way.
`code_label'
A `code_label' insn represents a label that a jump insn can jump
to. It contains one special field of data in addition to the
three standard ones. It is used to hold the "label number", a
number that identifies this label uniquely among all the labels
in the compilation (not just in the current function).
Ultimately, the label is represented in the assembler output as
an assembler label `LN' where N is the label number.
`barrier'
Barriers are placed in the instruction stream after
unconditional jump instructions to indicate that the jumps are
unconditional. They contain no information beyond the three
standard fields.
`note'
`note' insns are used to represent additional debugging and
declarative information. They contain two nonstandard fields,
an integer which is accessed with the macro `NOTE_LINE_NUMBER'
and a string accessed with `NOTE_SOURCE_FILE'.
If `NOTE_LINE_NUMBER' is positive, the note represents the
position of a source line and `NOTE_SOURCE_FILE' is the source
file name that the line came from. These notes control
generation of line number data in the assembler output.
Otherwise, `NOTE_LINE_NUMBER' is not really a line number but a
code with one of the following values (and `NOTE_SOURCE_FILE'
must contain a null pointer):
`NOTE_INSN_DELETED'
Such a note is completely ignorable. Some passes of the
compiler delete insns by altering them into notes of this
kind.
`NOTE_INSN_BLOCK_BEG'
`NOTE_INSN_BLOCK_END'
These types of notes indicate the position of the beginning
and end of a level of scoping of variable names. They
control the output of debugging information.
`NOTE_INSN_LOOP_BEG'
`NOTE_INSN_LOOP_END'
These types of notes indicate the position of the beginning
and end of a `while' or `for' loop. They enable the loop
optimizer to find loops quickly.
`NOTE_INSN_FUNCTION_END'
Appears near the end of the function body, just before the
label that `return' statements jump to (on machine where a
single instruction does not suffice for returning). This
note may be deleted by jump optimization.
`NOTE_INSN_SETJMP'
Appears following each call to `setjmp' or a related
function.
`NOTE_INSN_LOOP_CONT'
Appears at the place in a loop that `continue' statements
jump to.
These codes are printed symbolically when they appear in
debugging dumps.
The machine mode of an insn is normally zero (`VOIDmode'), but the
reload pass sets it to `QImode' if the insn needs reloading.
Here is a table of the extra fields of `insn', `jump_insn' and
`call_insn' insns:
`PATTERN (I)'
An expression for the side effect performed by this insn.
`INSN_CODE (I)'
An integer that says which pattern in the machine description
matches this insn, or -1 if the matching has not yet been
attempted.
Such matching is never attempted and this field is not used on
an insn whose pattern consists of a single `use', `clobber',
`asm', `addr_vec' or `addr_diff_vec' expression.
`LOG_LINKS (I)'
A list (chain of `insn_list' expressions) of previous "related"
insns: insns which store into registers values that are used for
the first time in this insn. (An additional constraint is that
neither a jump nor a label may come between the related insns).
This list is set up by the flow analysis pass; it is a null
pointer until then.
`REG_NOTES (I)'
A list (chain of `expr_list' expressions) giving information
about the usage of registers in this insn. This list is set up
by the flow analysis pass; it is a null pointer until then.
The `LOG_LINKS' field of an insn is a chain of `insn_list'
expressions. Each of these has two operands: the first is an insn,
and the second is another `insn_list' expression (the next one in the
chain). The last `insn_list' in the chain has a null pointer as
second operand. The significant thing about the chain is which insns
appear in it (as first operands of `insn_list' expressions). Their
order is not significant.
The `REG_NOTES' field of an insn is a similar chain but of
`expr_list' expressions instead of `insn_list'. There are several
kinds of register notes, which are distinguished by the machine mode
of the `expr_list', which in a register note is really understood as
being an `enum reg_note'. The first operand OP of the `expr_list' is
data whose meaning depends on the kind of note. Here are the kinds
of register note:
`REG_DEAD'
The register OP dies in this insn; that is to say, altering the
value immediately after this insn would not affect the future
behavior of the program.
`REG_INC'
The register OP is incremented (or decremented; at this level
there is no distinction) by an embedded side effect inside this
insn. This means it appears in a `post_inc', `pre_inc',
`post_dec' or `pre_dec' RTX.
`REG_EQUIV'
The register that is set by this insn will be equal to OP at run
time, and could validly be replaced in all its occurrences by
OP. ("Validly" here refers to the data flow of the program;
simple replacement may make some insns invalid.)
The value which the insn explicitly copies into the register may
look different from OP, but they will be equal at run time.
For example, when a constant is loaded into a register that is
never assigned any other value, this kind of note is used.
When a parameter is copied into a pseudo-register at entry to a
function, a note of this kind records that the register is
equivalent to the stack slot where the parameter was passed.
Although in this case the register may be set by other insns, it
is still valid to replace the register by the stack slot
throughout the function.
`REG_EQUAL'
The register that is set by this insn will be equal to OP at run
time at the end of this insn (but not necessarily elsewhere in
the function).
The RTX OP is typically an arithmetic expression. For example,
when a sequence of insns such as a library call is used to
perform an arithmetic operation, this kind of note is attached
to the insn that produces or copies the final value. It tells
the CSE pass how to think of that value.
`REG_RETVAL'
This insn copies the value of a library call, and OP is the
first insn that was generated to set up the arguments for the
library call.
Flow analysis uses this note to delete all of a library call
whose result is dead.
`REG_WAS_0'
The register OP contained zero before this insn. You can rely
on this note if it is present; its absence implies nothing.
`REG_LIBCALL'
This is the inverse of `REG_RETVAL': it is placed on the first
insn of a library call, and it points to the last one.
Loop optimization uses this note to move an entire library call
out of a loop when its value is constant.
`REG_NONNEG'
The register OP is known to have nonnegative value when this
insn is reached.
For convenience, the machine mode in an `insn_list' or `expr_list' is
printed using these symbolic codes in debugging dumps.
The only difference between the expression codes `insn_list' and
`expr_list' is that the first operand of an `insn_list' is assumed to
be an insn and is printed in debugging dumps as the insn's unique id;
the first operand of an `expr_list' is printed in the ordinary way as
an expression.
File: gcc.info, Node: Calls, Next: Sharing, Prev: Insns, Up: RTL
RTL Representation of Function-Call Insns
=========================================
Insns that call subroutines have the RTL expression code `call_insn'.
These insns must satisfy special rules, and their bodies must use a
special RTL expression code, `call'.
A `call' expression has two operands, as follows:
(call (mem:FM ADDR) NBYTES)
Here NBYTES is an operand that represents the number of bytes of
argument data being passed to the subroutine, FM is a machine mode
(which must equal as the definition of the `FUNCTION_MODE' macro in
the machine description) and ADDR represents the address of the
subroutine.
For a subroutine that returns no value, the `call' RTX as shown above
is the entire body of the insn.
For a subroutine that returns a value whose mode is not `BLKmode',
the value is returned in a hard register. If this register's number
is R, then the body of the call insn looks like this:
(set (reg:M R)
(call (mem:FM ADDR) NBYTES))
This RTL expression makes it clear (to the optimizer passes) that the
appropriate register receives a useful value in this insn.
Immediately after RTL generation, if the value of the subroutine is
actually used, this call insn is always followed closely by an insn
which refers to the register R. This remains true through all the
optimizer passes until cross jumping occurs.
The following insn has one of two forms. Either it copies the value
into a pseudo-register, like this:
(set (reg:M P) (reg:M R))
or (in the case where the calling function will simply return
whatever value the call produced, and no operation is needed to do
this):
(use (reg:M R))
Between the call insn and this following insn there may intervene
only a stack-adjustment insn (and perhaps some `note' insns).
When a subroutine returns a `BLKmode' value, it is handled by passing
to the subroutine the address of a place to store the value. So the
call insn itself does not "return" any value, and it has the same RTL
form as a call that returns nothing.
File: gcc.info, Node: Sharing, Prev: Calls, Up: RTL
Structure Sharing Assumptions
=============================
The compiler assumes that certain kinds of RTL expressions are
unique; there do not exist two distinct objects representing the same
value. In other cases, it makes an opposite assumption: that no RTL
expression object of a certain kind appears in more than one place in
the containing structure.
These assumptions refer to a single function; except for the RTL
objects that describe global variables and external functions, no RTL
objects are common to two functions.
* Each pseudo-register has only a single `reg' object to represent
it, and therefore only a single machine mode.
* For any symbolic label, there is only one `symbol_ref' object
referring to it.
* There is only one `const_int' expression with value zero, and
only one with value one.
* There is only one `pc' expression.
* There is only one `cc0' expression.
* There is only one `const_double' expression with mode `SFmode'
and value zero, and only one with mode `DFmode' and value zero.
* No `label_ref' appears in more than one place in the RTL
structure; in other words, it is safe to do a tree-walk of all
the insns in the function and assume that each time a
`label_ref' is seen it is distinct from all others that are seen.
* Only one `mem' object is normally created for each static
variable or stack slot, so these objects are frequently shared
in all the places they appear. However, separate but equal
objects for these variables are occasionally made.
* When a single `asm' statement has multiple output operands, a
distinct `asm_operands' RTX is made for each output operand.
However, these all share the vector which contains the sequence
of input operands. Because this sharing is used later on to
test whether two `asm_operands' RTX's come from the same
statement, the sharing must be guaranteed to be preserved.
* No RTL object appears in more than one place in the RTL
structure except as described above. Many passes of the
compiler rely on this by assuming that they can modify RTL
objects in place without unwanted side-effects on other insns.
* During initial RTL generation, shared structure is freely
introduced. After all the RTL for a function has been
generated, all shared structure is copied by `unshare_all_rtl'
in `emit-rtl.c', after which the above rules are guaranteed to
be followed.
* During the combiner pass, shared structure with an insn can
exist temporarily. However, the shared structure is copied
before the combiner is finished with the insn. This is done by
`copy_substitutions' in `combine.c'.
File: gcc.info, Node: Machine Desc, Next: Machine Macros, Prev: RTL, Up: Top
Machine Descriptions
********************
A machine description has two parts: a file of instruction patterns
(`.md' file) and a C header file of macro definitions.
The `.md' file for a target machine contains a pattern for each
instruction that the target machine supports (or at least each
instruction that is worth telling the compiler about). It may also
contain comments. A semicolon causes the rest of the line to be a
comment, unless the semicolon is inside a quoted string.
See the next chapter for information on the C header file.
* Menu:
* Patterns:: How to write instruction patterns.
* Example:: An explained example of a `define_insn' pattern.
* RTL Template:: The RTL template defines what insns match a pattern.
* Output Template:: The output template says how to make assembler code
from such an insn.
* Output Statement:: For more generality, write C code to output
the assembler code.
* Constraints:: When not all operands are general operands.
* Standard Names:: Names mark patterns to use for code generation.
* Pattern Ordering:: When the order of patterns makes a difference.
* Dependent Patterns:: Having one pattern may make you need another.
* Jump Patterns:: Special considerations for patterns for jump insns.
* Peephole Definitions::Defining machine-specific peephole optimizations.
* Expander Definitions::Generating a sequence of several RTL insns
for a standard operation.
File: gcc.info, Node: Patterns, Next: Example, Prev: Machine Desc, Up: Machine Desc
Everything about Instruction Patterns
=====================================
Each instruction pattern contains an incomplete RTL expression, with
pieces to be filled in later, operand constraints that restrict how
the pieces can be filled in, and an output pattern or C code to
generate the assembler output, all wrapped up in a `define_insn'
expression.
A `define_insn' is an RTL expression containing four or five operands:
1. An optional name. The presence of a name indicate that this
instruction pattern can perform a certain standard job for the
RTL-generation pass of the compiler. This pass knows certain
names and will use the instruction patterns with those names, if
the names are defined in the machine description.
The absence of a name is indicated by writing an empty string
where the name should go. Nameless instruction patterns are
never used for generating RTL code, but they may permit several
simpler insns to be combined later on.
Names that are not thus known and used in RTL-generation have no
effect; they are equivalent to no name at all.
2. The "RTL template" (*note RTL Template::.) is a vector of
incomplete RTL expressions which show what the instruction
should look like. It is incomplete because it may contain
`match_operand' and `match_dup' expressions that stand for
operands of the instruction.
If the vector has only one element, that element is the template
for the instruction pattern. If the vector has multiple
elements, then the instruction pattern is a `parallel'
expression containing the elements described.
3. A condition. This is a string which contains a C expression
that is the final test to decide whether an insn body matches
this pattern.
For a named pattern, the condition (if present) may not depend
on the data in the insn being matched, but only the
target-machine-type flags. The compiler needs to test these
conditions during initialization in order to learn exactly which
named instructions are available in a particular run.
For nameless patterns, the condition is applied only when
matching an individual insn, and only after the insn has matched
the pattern's recognition template. The insn's operands may be
found in the vector `operands'.
4. The "output template": a string that says how to output matching
insns as assembler code. `%' in this string specifies where to
substitute the value of an operand. *Note Output Template::.
When simple substitution isn't general enough, you can specify a
piece of C code to compute the output. *Note Output Statement::.
5. Optionally, some "machine-specific information". The meaning of
this information is defined only by an individual machine
description; typically it might say whether this insn alters the
condition codes, or how many bytes of output it generates.
This operand is written as a string containing a C initializer
(complete with braces) for the structure type
`INSN_MACHINE_INFO', whose definition is up to you (*note
Misc::.).
File: gcc.info, Node: Example, Next: RTL Template, Prev: Patterns, Up: Machine Desc
Example of `define_insn'
========================
Here is an actual example of an instruction pattern, for the
68000/68020.
(define_insn "tstsi"
[(set (cc0)
(match_operand:SI 0 "general_operand" "rm"))]
""
"*
{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
return \"tstl %0\";
return \"cmpl #0,%0\"; }")
This is an instruction that sets the condition codes based on the
value of a general operand. It has no condition, so any insn whose
RTL description has the form shown may be handled according to this
pattern. The name `tstsi' means "test a `SImode' value" and tells
the RTL generation pass that, when it is necessary to test such a
value, an insn to do so can be constructed using this pattern.
The output control string is a piece of C code which chooses which
output template to return based on the kind of operand and the
specific type of CPU for which code is being generated.
`"rm"' is an operand constraint. Its meaning is explained below.