.ds CD \s-2CDL\s0 .TH CDM 10.1 UCDS .SH NAME cdm \- expand circuit macros .SH SYNOPSIS .B cdm [ .I options ] [ .I files ] .SH DESCRIPTION .PP .I Cdm reads a circuit described in \*(CD from the specified files. Macro calls are expanded and pin numbers are substituted for pin names. The expanded \*(CD is printed on the standard output. The error output is used for diagnostics. Note that names in \*(CD are restricted in length so that care should be taken to keep macro names short. The options available are: .TP 7 .B -f If any pin has a number and a name then .I cdm will use the number and not consult any library about the name. .TP 7 .BI -l file If .I file contains a .BR / , it is read as a library. Otherwise, .BI /usr/ucds/lib/lib/ file is read. If no library is specified then a standard library is read. .TP 7 .B -p List macro calls and definitions on the error output. .TP 7 .B -t Use the library (if any) to construct the .B \&.t lines (type to package translation) and the .B \&.tt lines (see .IR wcheck (10.1)). With this option, the "chips" file is no longer needed. .TP 7 .B \-v Print pin names as well as pin numbers in the \*(CD output. .SS "Macro Definitions" A macro definition corresponds to a file containing \*(CD. The name of the file for a definition .I d is .IB d .w\fR\|.\fP Such \*(CD files may be produced using .IR draw (10.1). Macros may have signal names as parameters. These parameters are identified by a pin name. The (set of) formal signal names associated with the macro pin is replaced when the macro is called with actual signal names, unless the formal signal name is global. In this latter case the actual and formal signal names must be the same. .SS "Macro calls" A chip of type .I d is a macro call if the file .IB d .w exists. If no such file exists, the chip is assumed to be primitive (as in, say, .BR 74S181 ), and if the type is surrounded by .B <> brackets, the chip is an input output connector. If .IB d .w exists then it is the definition of the macro .I d\|. Signal parameters of the macro are drawn in the same way as signals are connected to a chip. The pin name is the macro parameter name and the signal is the actual signal parameter. The name of the `chip' is the macro call name. A given macro can be called more than once, different instances being generated by different macro call names. Macros may not be called recursively. .SS Names Signal, chip and pin names consist of letters, digits and the characters .BR +-/$ . Names of individual signals in a bundle or of chips in a group may also be generated: .B name[ac-f] generates .BR "namea namec named namee namef" ; .and .B name<i:j> generates .BI name i \&... .BI name j where .I i and .I j are represented in decimal as strings, all the same length. Thus, .B BUS01 (and not .BR BUS1 ) is in the set BUS<0:15>. .LP The set of generated names can be separated by an amount .B k by writing .B name<i:k:k> and multiple indexing is allowed: .BR name<i:j><p:q> . Mixing the two generation methods is allowed. .BR BEWARE , the generated names are sorted alphabetically. .PP Signal and chip names have scope local to a macro definition unless the name contains a .BR / . A name containing a .B / is available throughout a circuit. Connector names are also available throughout a circuit. Signal and chip names used as formal parameters in a macro definition are replaced during macro expansion with the sequence of macro call names separated by .B / and ending with the actual parameter signal name. .SS "Name Matching" The names of pins, signals and chips may also be generated from patterns. A pin pattern searches all pin names for the chip type. Signal and chip patterns search all signal or chip names. Patterns have the following form. .nf \fL*\fR matches any sequence of characters \fL[...]\fR matches any of the characters enclosed \fL[x-y]\fR matches any character in the (ASCII) range \fLx\fR to \fLy\fR \fL?\fR matches a single character .fi .SS "Signal Expansion" A signal bundle may be connected to one or more chips (or macro) without having to write each chip or signal explicitly. In general each such array is expanded by generating the specified set of names. These names are then sorted alphabetically. The first signal is connected to the first pin of the first chip. Subsequent signals are connected to successive pins. If no more pins exists then the first pin on the next chip is used. The signal bundle must always end on the last pin of a chip and there must be no signals unattached at the end. .SH SEE ALSO .IR cdmglob (10.1)