V10/vol2/Ucds/ucds.ind

chip type, ucds,  1-2
chips, ucds,  1-2	XXG
Circuit Design Language, ucds,  2
Circuit Design System, ucds,  1	XXG
multiwire, ucds,  1	XXG
PAL equations, ucds,  1
ucds, .brd,  2
ucds, .e,  1-3
ucds, .fx,  2
ucds, .j file,  3
ucds, .p,  1-3
ucds, .pins,  1-4
ucds, .pkg,  2
ucds, .pos,  2
ucds, .t lines,  4
ucds, .w ,  3
ucds, .wr,  2
ucds, .wx,  1-2, 4
ucds, /GND,  3
ucds, /VCC,  3
ucds, CDL,  2
ucds, cdm,  3
ucds, Cdmglob,  1, 3
ucds, chip type,  1-2
ucds, Circuit Design Language,  2
ucds, fizz cvt,  2
ucds, fizz place,  2
ucds, I/O connector,  1, 3
ucds, jraw,  1-3
ucds, lde,  1
ucds, lde format,  1
ucds, logical part,  1
ucds, Methodology,  1
ucds, Mkpins,  1
ucds, net name,  1-3
ucds, package type,  1-2, 4
ucds, PAL equations,  1
ucds, physical part,  1
ucds, pin holes,  1
ucds, pin name,  1-4
ucds, pin number,  1, 3
ucds, rework,  2
ucds, Signal Bundles and Macros,  2
ucds, special-signal nets,  1
ucds, special-signal pins,  1
ucds, text string,  2-3
wire-wrap, ucds,  1