[COFF] Porting the SysIII kernel: boot, config & device drivers

[Ralph Corderoy]

Hi Branden,

> Paul Ruizendaal wrote:
> > That was my immediate pain point in doing the D1 SoC port.
> > Unfortunately, the manufacturer only released the DRAM init code as
> > compiler ‘-S’ output and the 1,400 page datasheet does not discuss
> > its registers. Maybe this is a-typical, as I heard in the above
> > keynote that NXP provides 8,000 page datasheets with their SoC’s.
...
> I don't think it's atypical.  I was pretty annoyed trying to use the
> data sheet to program a simple timer chip on the ODROID-C2
...
> OS nerds don't generally handle procurement themselves.  Instead,
> purchasing managers do, and those people don't have to face the pain.
...
> Data sheets are only as good as they need to be to move the product,
> which means they don't need to be good at all, since the people who
> pay for them look only at the advertised feature list and the price.

I think it comes down to the background of the chip designer.  I've
always found NXP very good: their documentation of a chip is extensive;
it doesn't rely on referring to external source code; and they're
responsive when I've found the occasional error, both confirming the
correction and committing to its future publication.

On the other hand, TI left a bad taste.  The documentation isn't good
and they rely on a forum to mop up all the problems but it's pot luck
which staffer answers and perennial problems can easily be found by a
forum search, never with a satisfactory answer.

My guess is Allwinner, maker of Paul's D1 SoC, has a language barrier
and a very fast-moving market to dissuade them from putting too much
effort into documentation.  Many simpler chips from China, e.g. a JPEG
encoder, come with a couple of pages listing features and some C written
by a chip designer or copied from a rival.

In my experience, chip selection is done by technical people, not
procurement.  It's too complex a task, even just choosing from those of
one supplier like NXP, as there is often a compromise to make which
affects the rest of the board design.  That's where FPGAs have an
allure, but unfortunately not in low-power designs.

-- 
Cheers, Ralph.