vtserver

[Steven M. Schultz]

Hi -

> From: James Lothian <simul8 at simul8.demon.co.uk>
> 
> Hmm.. I seem to remember, from when I was thinking about rolling my own 
> 11 OS a few years ago, that the /34 differs from most of the other
> mid-range 11s in automatically restoring the CPU registers on a page fault. I

	It's not the automatically restoring that is the problem - the /34, /40
	(/60, etc) lack the MMU registers that record by how much the cpu
	registers have incremented/decremented at the time an instruction has
	faulted. SSR1 and SSR2 located at 0177574 and 0177576 respectively.

	From the module which handles the instruction restart (mch_backup.s):

* 11/40 version of backup, for use with no SSR1 and SSR2.  Actually SSR1
* usually exists for all processors except the '34 and '40 but always
* reads as zero on those without separate I&D ...

	What is a dozen lines of code if those registers exist turns into
	over 300 lines and even then there is no guarantee (fortunately the
	C compiler does not generate the sequences that can not be handled)
	it will work.

	What's instruction restart used for?  The most common case is growing
	the stack.  The stack for a process starts out small and then kernel
	will automatically extend it downwards IF an instruction faults when
	accessing the stack area:


		sub	$N,sp
		mov	$xxx, XX(sp)
		mov	-(r4), X(sp)

	for dealing with local variables in a function.  The other case
	is when calling a function:

		mov	(r0)+, -(sp)
		mov	$xxx, -(sp)
		jsr	pc, function

	If the reference to (sp) is made and the instruction faults the
	kernel will determine if the current stack needs to be extended.  It
	will then restart the faulted instruction - but to do that it needs
	to know what other registers ('r0', 'r4', etc...) might have been
	already changed so that it can back out those changes before 
	restarting the instruction.

	In the case of the 11/44, 70, 73, etc there are MMU registers that
	will record the fact that "R0" or "r4" or whatever was changed by
	2 or not.  On the /34 and /40 that capability does not exist and
	the kernel can not _always_ guarantee things will work.  MOST of the
	time it will but...

	Interestingly enough there is a difference between the KDJ-11 (11/73)
	family and the other 11s which have the SSR1, and 2.   From the
	bug report and fix for 2.11BSD (update #150):

	"The problem  is that the KDJ-11 processes the double word store
        of the 'movfi' differently than the 11/44 or 11/70.  On other
        systems (such as the 11/44) the first word is stored successfully
        at 0175000 then the program faults when trying to access 0174776
        but SP is left at 0174776 with SSR1 (memory management
        status register 1) indicating that 'sp' was decremented by 4.  The
        kernel adjusts 'sp', grows the stack and restarts the instruction.
        The 'movfi' then completes successfully.

        On a KDJ-11 cpu the story is different.  The fault is generated
        as expected BUT 'SP' IS STILL 0175002!  The kernel sees that 'sp'
        is still within the "valid stack region" and DOES NOT grow the
        stack at all.   SSR1 indicates that no registers were modified
        so the kernel does no adjustment of 'sp'.  The instruction is
        NOT restarted and a SIGSEGV signal is sent to the program.

        The problem appears to be only when doing FP instructions, fixed point 
        operations do not experience any difficulty.  The instruction
        "cmp -(sp),-(sp)" for example is handled correctly."

	Steven Schultz
	sms at moe.2bsd.com

Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id GAA18253
	for pups-liszt; Sun, 17 Oct 1999 06:08:29 +1000 (EST)