Help: PDP-11 instruction classification

johnh at johnh at
Wed May 10 10:37:51 AEST 2000

The 11/45 has the base instruction set, plus EIS (MUL, DIV, ASH, ASHC, SPL,
SOB, XOR, MARK, SXT, RTT). This was standard with the CPU, and the optional
floating point unit (another 4 cards in the backplane) added the floating
point instruction set.

The 11/40 has billions (Carl Sagans) of options. The minimal processor had
the base set, plus SOB, MARK, RTT, XOR and SXT. Processor options added extra
microcode and extra shift registers and counters to the data path.

	Option	Description
	KE11-E	EIS instruction set (ASH, ASHC, DIV, MUL)
	KE11-F	FIS instruction set (FDIV, FMUL, FADD, FSUB)
	KJ11-A	Stack limit register
	KT11-D	Memory management
	KW11-L	Line time clock

The processor options had dedicated slots, but lots of jumpers have to be
changed to enable them. Note that there are just four floating point
instructions (not directly compatible with any FPP instruction), and they
are not very PDP-11 like in their behaviour. The instructions have a three bit
address field to specify a register. The register points to a 'floating point
stack frame' that contains the arguments for the instruction in memory. The
floating point number format is the same as FPP.

When the original LSI-11 came out, it was modeled on 11/40, again with the
base instructions, plus SOB, MARK, RTT, XOR and SXT. EIS and FIS were options
in 'Microm Chips' (extra microcode). There was no memory management options
and it lacked an addressable PSW (processor status word) and switch register

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