[TUHS] PWB contributions

Random832 random832 at fastmail.com
Tue Nov 10 14:11:42 AEST 2015

"Jeremy C. Reed" <reed at reedmedia.net> writes:
> By the way, I don't have experience with the CR3 control register, and
> don't really understand what it means from the hardware perspective.

If I understand correctly, it's not hardware, it's part of the kernel
tty driver. There's a two bit field in the stty flags, for selecting a
delay mode. The purpose of the delay was to allow the terminal time to
process it (i.e. to physically move the carriage, for a printing
terminal) - the kernel would wait before sending more characters.

As can be seen in tty.c (link below), CR1 caused a delay of 5 units, and
CR2 a delay of 10 units. CR3 had no meaning in the standard kernel, and
so some custom version of the kernel could have interpreted it to have
some other meaning.


It's not clear where this was actually done. The 3BSD kernel used
CR3 to indicate that (if I read it correctly) a number of padding
characters depending on the column position should be inserted.

P.S. Somewhat confusingly, searching for "CR3" finds a page about
"control registers" of the _intel 386_, of which CR3 has something to do
with "paging" in the virtual memory sense of the word. This has nothing
to do with the topic under discussion.

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