[TUHS] SPARC is CRAPS spelled backwards.
jnc at mercury.lcs.mit.edu
Mon Sep 24 21:48:04 AEST 2018
> From: Paul Winalski
> In general, a CISC instruction set encoding can express the same
> algorithm more compactly than a RISC instruction set.
I have often pointed to memory bandwidth as one of the key factors in the
evolution of CISC and RISC. When it was low, compared to CPU speeds (most of
the core era), CISC made sense. When it increased (with DRAM), RISC made more
sense, because it allowed CPUs to run faster (via simpler instructions).
Caching made the picture a little more complex; and today, with the incredible
mismatch between memory speeds and CPU speeds, caching dominates, whether you
have RISC or CISC.
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