[TUHS] Encoding an ISA: Random Logic vs. Control Stores

[Paul Ruizendaal]

For DEC memo’s on designing the PDP-11 see bitsavers:

http://www.bitsavers.org/pdf/dec/pdp11/memos/

(thank you Bitsavers! I love that archive)

Ad van de Goor (author of a few of the memo’s) was my MSc thesis professor. I recall him saying in the early 80’s that in his view the PDP-11 should have been an 18-bit machine; he reasoned that even in the late 60’s it was obvious that 16-bits of address space was not enough for the lifespan of the design.

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For those who want to experiment with FPGA’s and ancient ISA’s, here is my plain Verilog code for the TI 9995 chip, which has an instruction set that is highly reminiscent of the PDP-11:
https://gitlab.com/pnru/cortex/-/tree/master

The actual CPU code (TMS99095.v) is less than 1000 lines of code.

Paul