[TUHS] quick question on PDP-11 addressing

[Clem Cole via TUHS]

As a PS and for completion, consider the registers:

Register Usage Conventions

   - R0 and R1 (Accumulators/Return Values): These are used as temporary
   scratchpads for expression evaluation. When a function returns a value, it
   is placed in R0; if the return value is a 32-bit long, the high-order bits
   are placed in R0 and the low-order bits in R1.
   - R2, R3, and R4 (Local Variables): These are used for local variables
   within a function. By convention, their values must be saved to the stack
   upon entering a procedure and restored before exiting, ensuring the calling
   function's data remains intact.
   - R5 (Frame Pointer / Environment Pointer): Known in UNIX as the FP, R5
   points to the current procedure's "activation record" or stack frame. It is
   used to access function arguments and local variables stored on the stack.
   - R6 (Stack Pointer / SP): This register tracks the top of the system
   stack. The hardware uses R6 implicitly during interrupts, traps, and
   subroutine calls (the JSR and RTS instructions).
   - R7 (Program Counter / PC): This register contains the memory address
   of the next instruction to be executed. Because it is a general register,
   it can be used with various addressing modes to provide immediate data and
   relative addressing



On Sun, May 3, 2026 at 4:35 PM Clem Cole <clemc at ccc.com> wrote:

> below
>
> On Sun, May 3, 2026 at 4:00 PM ron minnich via TUHS <tuhs at tuhs.org> wrote:
>
>> I was re-reading the KT-11 docs,
>
> A PDP-11 has 16-bit registers, so all addressing must be within a 64K
> boundary.
>
> There are a few versions of the MMU
>
>    - KS11 [CSS option for 11/20 -
>    http://gunkies.org/wiki/KS11_Memory_Protection_and_Relocation_option]
>    - KT-11B [CSS option https://gunkies.org/wiki/KT11-B_Technical_Manual
>    ]
>    - KT-11C,CD  for the 11/45 class [45, 50, 55) [
>    https://bitsavers.trailing-edge.com/pdf/dec/pdp11/1145/EK-KT11C-MM-005-KT11-C_CD_Memory_Management_Maintenance_Manual_1976.pdf
>    ]\
>    - For the 11/70, the MMU is builtin and the PARs are SW compatible
>    with KT-11-C
>    - and the KT-11D for the 40 class [40, 35]
>    https://gunkies.org/wiki/KT11-D_Memory_Management_Unit
>    - later 40 class processors (34, 34A and 60) use the KT-11A which is
>    software compatible with the KT-11D
>
> In all cases, regardless of operation mode (user, supervisor, kernel), the
> CPU has a 16-bit address (virtual) space of 32K words (64K bytes).  The MMU
> then maps those 16 bits into either an 18 or 22-bit physical address
> space.  On a 40-class processor, that means a total of 64K bytes of address
> space at a time, regardless of how the data in that address space is used.
> On the 45 and 70 class processors have the funky I/D bit, which gives 2
> separate 16-bit address spaces, instruction or data, so the MMU and OS can
> provide 2 64K bytes chunks of memory (for a total of 128K bytes) to the CPU,
> however, the '17th' which picks which of those two 64K byte hunks is
> being used is inferred from either and instruction or data fetch.
>
>
>
>
>> and got somewhat confused, and wanted
>> to verify my memory, that (absent Split I&D) user programs had virtual
>> addresses in the range 0-0xffff, and kernels the same: 0-0xffff.
>>
>> Thanks, I know this has been discussed before, but I'm giving a talk
>> at IWP9 next week and want to make sure I'm not missing something. The
>> KT-11 doc left me uncertain.
>>
>> You gotta love those old DEC docs, complete with SSI logic diagrams ...
>>
>