ISA bus limitations (Re: binary Mach distribution for 386)

[Thomas Hoberg]

In article <1991Jan31.010126.23088 at virtech.uucp>, cpcahil at virtech.uucp
(Conor P. Cahill) writes:
|> In article <296 at bigfoot.first.gmd.de> tmh at keks.FOKUS.GMD.DBP.DE
(Thomas Hoberg) writes:
|> >
|> >In article <1991Jan16.185851.2419 at ico.isc.com>, rcd at ico.isc.com (Dick
|> >Dunn) writes:
|> >|> Somewhere along the way to moving memory off the ISA bus, someone should
|> >|> have come up with a better DMA controller that also had a way to get to
|> >|> more memory.
|> >|> -- 
|> >But no DMA controller, however smart, can
|> >circumvent the fact that there are only 24 address lines on the ISA bus.
|> 
|> The address lines on the ISA bus don't matter in this case because most, 
|> if not all, 386 systems provide a second 32-bit memory bus for system 
|> memory.  It *should* be possible to find a DMA controller that will allow
|> you to move data from an ISA card to a 32 bit memory address.
|> 
Ok, I was thinking in terms of a bus mastering DMA controller, where the bus
master is generating the appropriate addresses...
Actually Intel itsself developed such a beast (maybe 82350?). Anyway SUN used
it in it's orphaned Roadrunner series of 386 Unix boxes. It has two modes:
1) PC compatible, 2) 32-bit. Because the DMA unit sits between the CPU and the
ISA bus, it can generate 32-bit addresses for the CPU thus obviating one of
the usual ISA limits. Bus mastering on that ISA bus was out, however, as was
the virtual DMA that SUN loves so much.
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