26 Aug
2020
26 Aug
'20
3:59 p.m.
From: John Cowan
That's always true on the PDP-11 and Vax ...
because the processor
architecture (which has pre-increment and post-decrement instructions,
but not their counterparts)
After Doug's message, I carefull re-read this, and I'm not sure it's
correct?
The PDP-11 has pre-decrement and post-increment, not the other way around (as
above) - unless I'm misunderstanding what you meant by those terms?
That's why:
*p++ = 0;
turns (if p is in R2) into
CLR (R2)+
R2 is used, and then incremented after it has been used.
Noel
26 Aug
26 Aug
4:09 p.m.
New subject: Memory management in Dennis Ritchie's C Compiler
On Wed, Aug 26, 2020 at 9:59 AM Noel Chiappa <jnc(a)mercury.lcs.mit.edu>
wrote:
This quirk of the PDP-11 is why I still prefer post-increment and
pre-decrement in my code... even though there's no chance in hades that my
code will ever run there...
Warner
From: John
Cowan
That's always true on the PDP-11 and Vax ...
because the processor
architecture (which has pre-increment and post-decrement
instructions,
but not their counterparts)
After Doug's message, I carefull re-read this, and I'm not sure it's
correct?
The PDP-11 has pre-decrement and post-increment, not the other way around
(as
above) - unless I'm misunderstanding what you meant by those terms?
That's why:
*p++ = 0;
turns (if p is in R2) into
CLR (R2)+
R2 is used, and then incremented after it has been used.
7:13 p.m.
New subject: Memory management in Dennis Ritchie's C Compiler
On Wed, Aug 26, 2020 at 12:09 PM Warner Losh <imp(a)bsdimp.com> wrote:
This quirk of the PDP-11 is why I still prefer
post-increment and
pre-decrement in my code... even though there's no chance in hades that my
code will ever run there...
Amen bro ...
4:14 p.m.
New subject: Memory management in Dennis Ritchie's C Compiler
You're right. Modes 2 and 3 are post-increment and post-increment deferred.
4 and 5 are pre-decrement and pre-decrement deferred.
On Wed, Aug 26, 2020 at 12:00 PM Noel Chiappa <jnc(a)mercury.lcs.mit.edu>
wrote:
From: John
Cowan
That's always true on the PDP-11 and Vax ...
because the processor
architecture (which has pre-increment and post-decrement
instructions,
but not their counterparts)
After Doug's message, I carefull re-read this, and I'm not sure it's
correct?
The PDP-11 has pre-decrement and post-increment, not the other way around
(as
above) - unless I'm misunderstanding what you meant by those terms?
That's why:
*p++ = 0;
turns (if p is in R2) into
CLR (R2)+
R2 is used, and then incremented after it has been used.
Noel
5:31 p.m.
New subject: Memory management in Dennis Ritchie's C Compiler
On Wed, Aug 26, 2020 at 11:59 AM Noel Chiappa <jnc(a)mercury.lcs.mit.edu>
wrote:
After Doug's message, I carefull re-read this, and I'm not sure it's
correct?
The PDP-11 has pre-decrement and post-increment, not the other way around
(as
above) - unless I'm misunderstanding what you meant by those terms?
Thank you! Post in haste, repent at leisure; but if I don't post in haste
these days, I won't be able to post at all....
John Cowan http://vrici.lojban.org/~cowan cowan(a)ccil.org
Almost all theorems are true, but almost all proofs have bugs.
--Paul Pedersen
1340
days inactive
1340
days old
4 comments
5 participants
participants (5)
-
Clem Cole -
Jim Geist -
jnc＠mercury.lcs.mit.edu -
John Cowan -
Warner Losh