My memory failed me: the part numbers were Z8001/Z8002 for the original and Z8003/Z8004
for the revised chips (segmented/unsegmented).
Hence it is unlikely that the Onyx had any form of demand paging (other than extending the
stack in PDP11-like fashion).
A somewhat comparable machine to the Onyx was the Zilog S8000. It ran “Zeus”, which was
also a Unix version:
Instead of the MMU described below it used the Zilog segmented MMU chips, 3 of them. These
could be used to give a plain 16 bit address space divided in 3 segments, or could be used
with the segmented addresses of the Z8001. The approach used by Onyx seems much cleaner to
me, and reminiscent of the MMU on a DG Eclipse.
I think the original chips were the Z8000 (unsegmented) and the the Z8001 (segmented).
These could not abort/restart instructions and were replaced by the Z8002 (unsegmented)
and Z8003 (segmented). On these chips one could effectively assert reset during a fault
and this would leave the registers in a state where a software routine could roll back the
If the sources to the Onyx Unix survived, it would be interesting to see if it used this
capability of the Z8002 and implemented a form demand paging.
Last but not least, the Xenix overview I linked earlier
) shows Xenix ports to 4 other Z800
machines: Paradyne, Compucorp, Bleasedale and Kontron; maybe all of these never got to
Date: Tue, 21 Jan 2020 21:32:51 +0000
From: Derek Fawcus <dfawcus+lists-tuhs(a)employees.org>
To: The Unix Heritage Society mailing list <tuhs(a)tuhs.org>
Subject: [TUHS] Onyx (was Re: Unix on Zilog Z8000?)
Content-Type: text/plain; charset=us-ascii
On Tue, Jan 21, 2020 at 01:28:14PM -0500, Clem Cole wrote:
The Onyx box redated all the 68K and later Intel
or other systems.
That was a fun bit of grubbing around courtesy of a bitsavers mirror
It seems they started with a board based upon the non-segmented Z8002
and only later switched to using the segmented Z8001. In the initial
board, they created their own MMU:
Page 6 of:
Memory Management Controller:
The Memory Management Controller (MMC) enables the C8002 to perform
address translation, memory block protection, and separation of
instruction and data spaces. Sixteen independent map sets are
implemented, with each map set consisting of an instruction map and
a data map. Within each map there are 32 page registers. Each page
register relocates and validates a 2K byte page. The MMC generates
a 20 bit address allowing the C8002 to access up to one Mbyte of
So I'd guess the MMC was actually programed through I/O instuctions
to io space, and hence preserved the necessary protection domains.
Cute. I've had a background interest in the Z8000 (triggered by reading
a Z80000 datasheet around 87/88), and always though about using
the segmented rather than unsegmented device.
The following has a bit more info about the version of System III
ported to their boxes: