8 Mar
2001
8 Mar
'01
12:36 a.m.
Greg,
Thought about that too but the math doesn't work.
40+64 chips = 104
chips * 65536 bits per chip = 6815744 total bits.
6815744 doesn't divide cleanly by any of 9, 18, 19, 36, or 38
Right... 12 bits
of ECC seems a bit much. Dunno what that stuff is
about... weird! ;)
Fred
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Date: Wed, 7 Mar 2001 13:15:48 -0800 (PST)
From: Carl Lowenstein <cdl(a)mpl.ucsd.edu>
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To: greg(a)ciswired.com, pups(a)minnie.cs.adfa.edu.au
Subject: Re: [pups] Spares, et. al for 11/44 system
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Date: Tue, 6 Mar 2001 20:07:00 -0500 (EST)
From: "Gregory R. Travis" <greg(a)ciswired.com>
To: pups(a)minnie.cs.adfa.edu.au
Subject: [pups] Spares, et. al for 11/44 system
p.s. The Nat. Semi board is a bit strange. It has an area of
16x4 TI 64K-bit chips (i.e 64x64k/8 = .5MB) and another
area of 10x4 TI 64K-bit chips (i.e. .3MB). No matter
what I do, I can't do the math to get this board to
fit into a 256/512/1MB size. I ASSUME it's a .5MB
board, but what about the extra chips?
Nat.Semi. used to make ECC memory boards for the PDP11.
I had one once, it looks like you have one now. My arithmetic says 5
extra bits per 8-bit byte makes for single-error correcting, dual-error
detecting ECC on the byte level. Vaxes do it with 39 bits per 32-bit
word, Alphas do it with 72 bits per 64-bit word. Economy of scale.
As I remember, you could just ignore the ECC and it would work like
a standard parity memory board, except that it very rarely had any
parity errors.
carl
carl lowenstein marine physical lab u.c. san diego
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